GNSS RTL Design Engineer
Santa Clara Valley (Cupertino),California,United States
Hardware
4+ years' experience with power efficient GNSS RTL design with knowledge in modern design techniques and energy-efficient/low power logic design.
Strong foundation in computer architecture including one or more of the following: Bus fabric, especially APB/AHB/AXI, tiered memory systems, system debug architecture, power management with multiple power domains, integer and floating-point numeric units, high-speed data path and control units.
Proven track record for bringing logic designs into mass production and driving strong production test/QA methodologies is preferred.
Excellent verbal and written communication skills with a desire to understand how things work at the most fundamental level.
Experience with FPGA or emulation platform is a plus.
Description
In this role, you will develop signal processing intensive design for GNSS SoCs, including: - Microarchitecture definition - RTL design and implementation - GNSS Measurement Engine design with baseband knowledge - IC Synthesis, STA, timing methodologies and constraints - IP integration, RTL logic design, and verification support - Running tools to ensure lint-free and CDC clean design - Collaboration with system/algorithm and firmware team to ensure performance and power efficiency
Education & Experience
A MSEE with focus on digital communication, signal processing, or systems theory is required. A Ph.D. in related areas of signal processing is desired.
Additional Requirements
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